

// Tutorial for simulating the AMI06 technology using Ocean 
simulator lang=spectre

//====================================================
// Parameters
//====================================================
parameters pOutCap=10f

//====================================================
// Library Links
//====================================================
include "./crc_half.scs"

//====================================================
// Options
//====================================================
// NB - you need to set options in Ocean, because those options
// supercede any options in the netlist


//====================================================
// Sources - power supplies and inputs
//====================================================
V0 (vdd 0) vsource type=dc dc=pvdd

//====================================================
// CLK and Enable signal. Enable is required to be low
// at the first cycle and then high for 9 cycles.
//when simulating the leakage current, disable the first
//two lines and enable the last two lines
//====================================================
VCLK ( CLK 0 ) vsource type=pulse val0=0 val1=pvdd delay=0 rise=0.01n fall=0.01n width=Tclk*0.5 period=Tclk
VEN ( EN 0 ) vsource type=pulse val0=0 val1=pvdd delay=Tclk rise=0.01n fall=0.01n width=Tclk*9 period=Tclk*10

//VCLK ( CLK 0 ) vsource type=pulse val0=0 val1=pvdd delay=10*Tclk rise=0.01n fall=0.01n width=Tclk*0.5 period=Tclk
//VEN ( EN 0 ) vsource type=pulse val0=0 val1=pvdd delay=10*Tclk rise=0.01n fall=0.01n width=Tclk*9 period=Tclk*10

//====================================================
// Netlist sout_15 to sout_0 is the 16 bit output
// CRCHALF is the CRC circuit with 16 bit data word
// and 16 bit key word. Use vdd and vss to represent 1 and 0
//====================================================
C15 (sout_15 0) capacitor c=pOutCap m=1
C14 (sout_14 0) capacitor c=pOutCap m=1
C13 (sout_13 0) capacitor c=pOutCap m=1
C12 (sout_12 0) capacitor c=pOutCap m=1
C11 (sout_11 0) capacitor c=pOutCap m=1
C10 (sout_10 0) capacitor c=pOutCap m=1
C9 (sout_9 0) capacitor c=pOutCap m=1
C8 (sout_8 0) capacitor c=pOutCap m=1
C7 (sout_7 0) capacitor c=pOutCap m=1
C6 (sout_6 0) capacitor c=pOutCap m=1
C5 (sout_5 0) capacitor c=pOutCap m=1
C4 (sout_4 0) capacitor c=pOutCap m=1
C3 (sout_3 0) capacitor c=pOutCap m=1
C2 (sout_2 0) capacitor c=pOutCap m=1
C1 (sout_1 0) capacitor c=pOutCap m=1
C0 (sout_0 0) capacitor c=pOutCap m=1
CRCHALF (vdd vss CLK EN vss vss vdd vss vdd vss vss vdd vss vss vdd vss vdd vdd vss vdd vdd vdd vss vdd vss vss vdd vss vss vss vss vdd vdd vdd vss vdd sout_15 sout_14 sout_13 sout_12 sout_11 sout_10 sout_9 sout_8 sout_7 sout_6 sout_5 sout_4 sout_3 sout_2 sout_1 sout_0) CRCHalf
vvss (vss 0) vsource type=dc dc=0
